RTL Development of USB 3.0
Development and Verification of Soft IP Core of USB 3.0 Device in Verilog HDL
Role: BE thesis student, Co-developer.
Tools and skills used: Verilog HDL, ModelSim, Xilinx ISE.
About:
It was my Final Year Project (B.E. Thesis) and was completed under the supervision of EONSIL, Austin TX. In this research I, together with my group mates, developed a complete synthesizable RTL of SuperSpeed USB 3.0 device on Verilog HDL. I contributed in this project by developing the Physical (MAC) layer of USB 3.0 device and the Master Controller.
